
Requirements
============

Your job this year is to design a decimal floating point divider as 
defined in the IEEE 754-2008 using a subtractive method. Your divider 
should take as inputs two decimal floating point numbers encoded in the 
densely packed decimal format and generate as output the result of the 
division and the corresponding flags. 

Your design should be parameterized to work with either the decimal64 or 
decimal128 format as detailed below.

Givens and testing method
=========================
The provided test bench file (testbench.v) under the vlog_given 
subdirectory reads the input test vectors, applies them to the design, 
and generates an output file. 

The choice of the format to simulate is defined in the file dec64_128.v 
where you should choose either DECIMAL64 or DECIMAL128 but not both. 
Depending on the supported format chosen, the file defintions.v sets 
several parameters and the simulation begins.

The names of the input and output files are defined in the file 
io_files.v where you can change them to suite the path and names you use 
on your system. The default name of the output file from the simulation 
is either d64_div_out_hex.txt (for decimal64) or d128_div_out_hex.txt 
(for decimal128).

You should compare the output of the simulation with the provided 
correct results (d64_div_out_hex_corr.txt and 
d128_div_out_hex_corr.txt). Any differences between the design results 
and the correct output indicate the presence of errors in the design. 
For your reference, the human readable values of the inputs are given in 
d64_div_desc.txt and d128_div_desc.txt.

The remaining files within the vlog_given subdirectory implement parts 
of the design. Your job is to correct any errors in those files and 
complete the design in order to have a fully functioning design 
supporting either decimal64 or decimal128 based on the choice made in 
the file dec64_128.v.


Format of test vectors
======================

Please check the webpage (http://eece.cu.edu.eg/~hfahmy/arith_debug/) if 
you need more information on the test vectors beyond the brief 
description given here. They were transformed into the given format by 
the DecTool of SilMinds (http://www.silminds.com/resources/sw-tools).


Each line in the input test vectors file (d64_div_in_hex.txt for 
DECIMAL64 and d128_div_in_hex.txt for DECIMAL128) starts by a three bit 
code to indicate the rounding direction according to the 
following specification:

 000  => RNE = Round to Nearest ties to Even
 001  => RA  = Round Away from zero
 010  => RP  = Round toward Positive infinity
 011  => RM  = Round toward Minus infinity
 100  => RZ  = Round toward Zero
 101  => RNA = Round to Nearest ties Away from zero (round-half-up)
 110  => RNZ = Round to Nearest ties to Zero (round-half-down)

Then, the line gives the two operands according to the decimal64 (or 
decimal128 depending on the file) format of the IEEE Std754-2008 using 
the decimal DPD encoding. The numbers are written in human readable 
hexadecimal notation instead of binary to reduce the size of the files.

The corresponding correct output is given in the lines of the output 
file (d64_div_out_hex_corr.txt or d128_div_out_hex_corr.txt). Each 
output line gives the correctly rounded corresponding output (in 
hexadecimal) followed by a code to indicate the flags where 1 indicates 
that the flag is raised and 0 indicates that it is lowered. The flags 
are reported as inexact, invalid, overflow, and underflow.

The description file (d64_div_desc.txt or d128_div_desc.txt) gives a 
human (i.e. understandable) description of the operation, rounding 
direction, input operands, corresponding output, and flags for each line 
of the test cases. In the description file the rounding directions are 
written in an abbreviated manner where for example h> corresponds to the 
half-up (RNA) direction. The complete encoding is:

 0   RZ
 >   RP
 <   RM
 !0  RA
 =0  RNE
 h>  RNA
 h<  RNZ

and the flags are encoded as:

 x  inexact
 i  invalid
 o  overflow
 u  underflow.

Resources
=========
For your reference, I am including a copy of the last public draft of 
the standrad. This draft is technically the same as the final published 
one. It was slightly edited and minor corrections were made to it during 
the voting phase to approve the standard. 

A nice explanation of decimal floating point and its the two encodings 
is provided at (http://en.wikipedia.org/wiki/Decimal_Floating_Point) and 
(http://en.wikipedia.org/wiki/Densely_packed_decimal).

The page (http://speleotrove.com/decimal/) has many useful links and 
descriptions on decimal floating point.

Finally, a very good quick reference guide to Verilog is available at 
(http://www.sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf) in case 
you need it. Please restrict yourself to verilog commands supported by 
synthesis tools. (Check the reference guide above if in doubt.)


Submission
========== 
The project is due on Wednesday 21 December 2016 with a first milestone 
on Wednesday 07 December 2016. Please send me two things:

1. your verilog files (.v files **only**) as a single zip file

and

2. a one page (plain text) description of the major modifications and 
additions you did.

There is a bonus for those who submit earlier than the due date.

Enjoy!
