Two power efficient clock/data distribution techniques for the delay elements of
the polyphase decomposition comb filter is introduced. A general form for each
novel technique is developed with respect to the filter decimation factor. Applying
the proposed techniques on the polyphase comb filter results in a significant
reduction in its dynamic power consumption. Both modified and conventional
filters are implemented using spartan3 low power Field Programmable Gate
Arrays (FPGAs). Implementation results show that, applying the proposed
techniques results in a significant reduction of the dynamic power consumption
of polyphase comb decimation filters. In addition, the maximum allowable
sampling rate at which the polyphase filter can operate is increased. That in turns
increases the SNR of the ΣΔ modulator and improves its linearity. Finally, a
considerable reduction of the overall dynamic power consumption of a multistandard
SRC circuit in SDR receiver is achieved.