The trend of high-speed digital circuits is the increase in speed and density,
consume more current and power and to operate at lower voltage; that's why the
PDS design is challenging. In this thesis, we introduced a complete solution to
design a high-speed digital system PDS. Our design methodology covers the bulk
and decoupling capacitor value selection and placement as well as an accurate
methodology to check the full system PDS performance. Finally we used our
methodology to redesign state of the art memory sticks provided from JEDEC,
and the proposed design methodology gave better PDS performance with less
total capacitance.