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Home | Research | M.Sc. And Ph.D Thesis | Design and Implementation of a Novel Low-Power Security Processor

Design and Implementation of a Novel Low-Power Security Processor

Thesis Title: 
Design and Implementation of a Novel Low-Power Security Processor
Hala Ahmed Farouk Abdel Moneim Mohamed
Date of Birth: 
Thu, 15/12/1977
Previous Degrees: 
M.Sc. B.Sc.
Registration Date: 
Sat, 09/04/2005
Awarding Date: 
Sat, 20/08/2011
External Supervisors: 

Dr. Ahmed Abou El Farag (Arab Academy for Science and Technology)


Prof. Dr. Mohamed Adeeb Riad Ghonaimy (Ain Shams University)
Prof. Dr. Magdy El-Soudani
Prof. Dr. Mahmoud Taher El-Hadidi

Key Words: 

Security Processors, GALS, ISA, Side-Channel Attacks, FPGA


The past two decades have witnessed a revolution in the use of electronic devices in our daily activities. Increasingly, such activities involve the exchange of personal and sensitive data by means of portable and light weight devices. This implied the use of security applications in devices with tight processing capability and low power budget. Meanwhile, general-purpose processors cannot cope with the needs of encryption algorithms nor with operations involving processing and storage of private and sensitive data, which require high degree of protection and privacy. For this reason, researchers have been working recently to develop special-purpose security processors, exhibiting high performance, adaptable functionality, immunity against attacks, and low power consumption. This thesis presents the details of the design, simulation, and performance evaluation of a novel low-power security processor that meets the above stated goals. It uses a Globally-Asynchronous Locally-Synchronous (GALS) internal structure and follows the data-flow architectural model. The thesis explains the underlying concepts that lead to dividing the processor into 6 zones, identifies the functional units that each zone comprises, describes the frame structure of data and control packets (including the header format) that are exchanged inside the processor, specifies the procedure used for designing the wrappers that enclose each zone, proposes the list of commands used for implementing the Processor Programming Interface (PPI), deploys the new processor to implement the three well-known security algorithms (namely: AES, RSA, and EEC), and finally performs evaluation of the new processor throughput and immunity against side-channel attacks. Simulation results showed that the GALS-based Low-Power Security Processor (LPSP) offers twice the throughput of the LEON3 processor and half the power consumed by the CoreMP7 processor. Moreover, the GALS concept – coupled with an extra feature of randomizing the data traffic between the internal function units - has increased the immunity of the processor against the DPA attacks by at least 35% than the specialized AES circuits.