The frequency divider is an essential and critical building block in frequency
synthesizers to prescale output frequency. In addition, some RF communication
transceivers require quadrature signals for I/Q (de) modulation. The generation
of such signals can be achieved by I/Q frequency dividers. In this thesis, several
topologies of I/Q frequency dividers are investigated. Three architecture are
chosen for simulation and evaluating their performance characteristics. Two of
them are new architecture using ILFD method based on BS_QVCO, and NMOSPMOS
oscillator topology. The other is the CML divider with active and resistive
load. The simulation results and performance characteristics show that, the CML
dividers consume less power, and can be used up to 8 GHz. For applications
above 8 GHz, the ILFD can be used with less operating frequency range and
higher power consumption.