Multiple input multiple-output (MIMO) technology has emerged as a promising technology for achieving
high data rates of next generation wireless communication systems. However, MIMO systems suffer from
the complexity of their maximum likelihood detector (MLD), which grows exponentially with the number
of transmit and receive antennas. Recently, the sphere decoding (SD) algorithm enabled the
implementation of efficient MIMO decoders that achieve MLD performance together with reduced
complexity. Instead of the exhaustive search over all possible transmitted symbols, the SD algorithm
reduces the complexity by searching only over a finite number of symbols within a circle of radius R
centered at the received vector. However, the SD algorithm experiences variable throughput problems as
the search radius R for each symbol depends on the noise levels and the channel coefficients affecting the
symbol. Moreover, the sequential search results in hardware implementations that are not fully pipelined.
To alleviate these problems, the fixed sphere decoding (FSD) algorithm was recently proposed that
achieves fixed throughput performance and enables fully-pipelined hardware by performing fixed
number of operations, independent of the noise level, to detect each symbol. The FSD algorithm is
performed in two stages. The first one is a preprocessing stage that incorporates a QR decomposition of
the MIMO channel matrix. This preprocessing allows for employing a tree-based search algorithm at the
second stage that finds the optimal symbol. In this thesis, we present an efficient FPGA prototype of the
FSD that implements an efficient QR decomposition of the channel matrix for a MIMO system using
CORDIC array techniques followed by the tree-based search algorithm. This prototype provides an
improved hardware implementation in terms of area and throughput compared to up-to-date published
results in the literature. The FPGA implementation is incorporated with a MATLAB simulation model of
an OFDM based MIMO system to validate the hardware design. As a case study, we employed the FSD in
the receiver of the IEEE802.16e WiMAX MIMO systems. The IEEE 802.16e standard supports three
types of MIMO space time codes (STC), referred to in the standard by matrix A, B, and C, that achieve
different levels of throughput and diversity depending on the quality of the MIMO channels. We have
shown how a single FSD can be used to decode the different STC schemes by adaptively processing the
received signal according to the STC type. Our results indicate that this FPGA implementation achieves
the throughput values that satisfy the requirements of the WiMAX technology.