In this thesis, I propose a novel fully integrated scalable multi-channel clock and
data recovery design that realizes significant area and power savings to bring
Tbps (tera-bits-per-second) communication within reach and make it an
integrable function at the periphery of high-speed systems and SoCs. The
proposed chip design exploits the synchrony of multiple point-to-point optical or
inter-chip links and constructs a novel scalable architecture that saves on chip
area by using a single VCO block to drive multiple phase detection loops. A highlevel
system model has been developed in Verilog-A to provide an early proof of
concept and to drive the top-down design process. The proposed architecture
exhibits asymptotically zero jitter peaking and allows independent optimization
of VCO jitter transfer and data jitter transfer. Zero jitter peaking is a highly
desirable merit in long-haul communications networks that string long chains of
repeaters. Moreover, the VCO jitter is becoming an increasingly significant
limitation on high-speed PLLs because VCO jitter transfer trades off with data
jitter transfer on which data communications standards usually put stringent
requirements, hence the importance of decoupling VCO jitter transfer from data
jitter transfer.