In this thesis, we develop functional-level power lTlodels and investigate several software optimization techniques for embedded-processor systems. As a specific ex.ample, we
consider the powerful Tex.as Instruments C64l6T OSP processor. We analyze the power consumption contributions of the different functional units of this OSP. We assess the
effect of the compiler performance optimizations on the energy and power consumption. Moreover, we explore the impact of two special architectural features of this OSP;
namely Software Pipelined Loop (SPLOOP) and the SIMO capabilities, on the energy and power consumption. We also characterize the application-architecture correlation for
our targeted architecture. The PCA multivariate statistical technique is employed to visualize the black box impact of the compiler and the hardware architecture over the
software applications. This is achieved withJhe aid of biplots which is depicted in our analysis in such a way, so that it can show the maximum association between the
application and the underlying hardware architecture. Hence, it answers the question whether a given hardware architecture is an appropriate choice for a given software
application or not . The currently-available compiler optimization techniques are handicapped for power optimization due to their partial perspective of the algorithms and due
to their limited modifications to the data structures. On thc contrary, other software optimization techniques, like source code transformations, can exploit the full knowledge of
the algorithm characteristics, with the capability of modifying both data structures and algorithm coding. Furthermore, inter-procedural optimizations are envisioned. Hence,
we investigate several loop, data and procedural source code transformations fi'om the power and energy perspectives . Based on our results and as a step towards a poweraware
optimizing compiler, we can recommend the following recommendations for programmers and compiler designers .First ،the programmers, targeting the C6000 OSP
family, are strongly recommended to compile and optimize their programs by invoking the optimization level -03 while disabling the SPLOOP feature (-mu) in conjunction with
the utilization of SIMO capabilities via the employment of suitable intrinsic functions . Second ،we recommend the compiler designers to pay more attention to the circular
(modulo) and bit reverse addressing schemes which are rarely utilized by the compiler. Also, developers of power-aware compilers need to embcd a functional level power
consumption model for the target processor in their compiler software .In addition, they should utilize the power-aware source code transformations.