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Arithmetic operations debugging and verification |
تنقيح العمليات الحسابية والتحقق منها |
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Project descriptionWe aim to produce high quality test vectors for the various arithmetic operations. A test vector is the set of inputs (operands and rounding direction if needed) and the corresponding correct outputs (result and flags if any). High quality means that the test vectors are not just randomly selected but they are rather directed to uncover potential problems in the design. The project started with the verification of floating point operations. |
وصف المشروعيهدف المشروع لانتاج متجهات اختبار عالية الجودة للعمليات الحسابية. نعني بمتجه الاختبار مجموعة القيم التي تتم عليها العملية مع طريقة الجبر للكسور المستخدمة والناتج المقابل مع أي تحذيرات قد تظهر. ونعني بعالية الجودة أن متجهات الاختبار ليست عشوائية بل تم إنتاجها لتكشف عن مشاكل محتملة في التصميمات. بدأ المشروع بالتحقق من العمليات على الأعداد الكسرية. |
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The quality of our work speaks of itself. Our test vectors discovered bugs in several designs:
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تتحدث جودة متجهاتنا عن نفسها فقد اكتشفت أخطاء في عدد من التصميمات:
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Project historyThis research project started in November 2009 at the Electronics and Electrical Communications Department, Faculty of Engineering, Cairo University. This project is still under progress. It grew out of collaboration on a research project with SilMinds funded by the RDI program of the Egyptian Ministry of Higher Education and the European Union. A sequel joint project with SilMinds funded by the ITAC program of the Egyptian Ministry of Communications and Information Technology allowed us to continue the work. |
تاريخ المشروعبدأ هذا المشروع في نوفمبر 2009 في قسم هندسة الإلكترونيات والاتصالات الكهربية بكلية الهندسة في جامعة القاهرة ولا يزال العمل جاريا فيه. نشأ المشروع من خلال أبحاث مشتركة مع شركة سيلميندز ممولة من برنامج الأبحاث والتطوير والابتكار التابع لوزارة التعليم العالي والبحث العلمي المصرية والاتحاد الأوروبي. مكننا مشروع بحثي آخر مع شركة سيلميندز ممول من وزارة الاتصالات وتكنولوجيا المعلومات المصرية من استكمال العمل. |
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Project group membersCurrent members working on the project are:
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أعضاء فريق المشروعأعضاء المشروع حاليا هم:
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PublicationsAmr finished his MSc thesis in June 2011. So far, two papers are published:
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Try our test vectorsThe first work on our test vectors was inspired by the FPGen project of IBM. The test vectors files follow the same syntax as in that project. Specifically, each line represents a single test vector with parts separated by spaces as follows:
Decimal FP operationsFor an explanation of the relevant models used to generate the test vectors please refer to the publications section, especially the MSc thesis of Amr Sayed-Ahmed. Each zip file below archives a directory with files for the operation indicated by the file name and dated as in the name as well. The md5sum files hold checksum values for the corresponding files. The DecTool of SilMinds is able to parse our files and generate the corresponding hexadecimal or binary strings necessary for circuit simulation. The files provided below with test vectors for the decimal FP operations are copyrighted to Amr Sayed-Ahmed and Hossam A. H. Fahmy. They are provided as is without any implied warranties. The persons who download the files are free to use them for any purpose under their own responsibilities. The copyright owners provide the files in the hope that they will be useful to others but give no guarantees. We would appreciate if you reference our work and give us credit for it.
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Page designed and maintained by Hossam A. H. Fahmy. This page has Valid XHTML 1.0 (strict) and Valid CSS! |
القائم بتصميم وتحديث الصفحة حسام علي حسن فهمي هذه الصفحة تتبع مواصفات XHTML 1.0_strict و CSS! |