In this thesis, we analyze the use of the signed digit (SD) number system and its
advantages in achieving simultaneously high speed and low EDP arithmetic
circuit. The hybrid signed digit (HSD) system is presented as an intermediate
solution between the SD system and the conventional system. A HSD adder
architecture is analyzed, a new HSD adder/subtractor and a modified version of
this circuit are proposed. Furthermore a third HSD adder/subtractor from the
literature is analyzed. A complete arithmetic unit based on the new circuit is also
proposed and analyzed including the conversion to and from the conventional
system. We recommend using a higher redundancy for applications targeting a
shorter delay, a smaller ADP, and a smaller EDP. For low area applications,
conventional architectures are the best choice